Counter-based digital pulse width modulator (DPWM) and digital delay locked loop (DLL) are the common implementations for delay lines. However, as speed requirements for delay lines increase, these implementations can require costly resources for reliable implementation. Counter-based DPWMs become impractical for delay lines as speed requirements increase because of the need for even higher speed clocks. For example, if one percent of a the DPWM resolution is required in a 1 megahertz (1 MHz) switching frequency converter, a 1 gigahertz system clock is needed which can make the implementation impractical for a given application.
A DLL based solution can be low power but can consume a large circuit area. In addition, the delay generated is the integer multiple of one cell delay. At current 0.18 um process, the delay of one cell (e.g., inverter) is limited to about 80 ps and can vary by process, temperature and voltage. Hence, the increment or decrement of the delay is large and can cause nonlinearity.